In a conventional SRAM cell as shown in FIG. 1(a), double bit lines have been used for read and write accesses--read and write operations are done via the same pair of bit lines. Therefore, while designing two-port memory IC with simultaneous read and write capability, two more pass transistors and an extra pair of bit lines are needed to be incorporated into the memory cell. As a result, the size of the memory cell is increased substantially. If the memory cell structure can be simplified to provide the operation with only one bit line for read and the other bit line for write, the size of this memory cell can be reduced a lot for implementing two-port VLSI SRAM. The difficulty of using the conventional SRAM cell with single-bit-line write access can be perceived from FIG. 1(b). As shown in FIG. 1(b), if logic-1 is to be written from the left bit line WBL via the pass transistor M.sub.N1 into the left side of the memory cell (node n1), where logic-0 is originally stored. During the write-in operation, the voltage at node n1 cannot be raised to exceed V.sub.dd -V.sub.TN by the write bit line WBL, where V.sub.dd is the power supply voltage and V.sub.TN is the threshold voltage of the pass transistor M.sub.N1. In addition, since the ratioed-logic structure, which is made of the NMOS devices M.sub.N1 and M.sub.N3 in the memory cell and the PMOS device M.sub.P3, which is the driver of the bit line WBL, plus the fact that the electron mobility of the NMOS devices is larger than the hole mobility of the PMOS device, the voltage of node n1 is difficult to be raised during the single-bit-line write-logic-1 operation. As a result, the conventional SRAM cell structure cannot be used for two-port memory circuits with the single-bit-line write-logic-I operation. Although several techniques [T. S. Yang, M. A. Horowitz, and B. A. Wooley, "A 4ns 4Kx1 bit Two-Port BiCMOS SRAM," IEEE Journal of Solid-State Circuits, Vol. 23, October 1988, pages 1030-1040; M. Ukita, S. Murakami, T. Yamagata, H. Kuriyama, Y. Nishimura, and K. Anami, "A Single-Bit-Line Cross-Point Cell Activation (SCPA) Architecture for Ultra-Low-Power SRAM's," IEEE Journal of Solid-State Circuits, Vol. 28, No. 11, November 1993, pages 1114-1118] have been applied to resolve this difficulty, the penalty cannot be justified for realizing two-port VLSI SRAM.